This invention relates to signal detect circuitry for use in a passive Gigabit Interface Converter (GBIC) module.
Fibre Channel and Gigabit Ethernet are high speed data transfer interfaces that can be used to interconnect workstations, mainframes, supercomputers and storage devices. Supporting numerous channel and network Upper Level Protocols (ULPs), Fibre Channel allows faster data transfer over longer distances between a larger number of devices or communication points. The standard combines attributes of a channel with attributes of a network, thus providing a general transport vehicle for ULPs such as the Small Computer System Interface (SCSI), the Intelligent Peripheral Interface (IPI), the High Performance Parallel Interface (HIPPI), the Internet Protocol (IP), Ethernet (IEEE 802.3) and the Asynchronous Transfer Mode (ATM). Accommodating the pattern of ever increasing data rates, Fibre Channel is a scalable interconnect standard that considers all aspects of speed, length and media (copper and fiber). Fibre Channel development is focused on data transfer at 1.0625 Gbits/sec with provisions for 2.125 Gbits/sec and 4 Gbits/sec.
AMP Incorporated of Harrisburg, Pa., Compaq computer Corporation of Houston, Tex., Vixel Corporation of Bothell, Wash. and Sun Microsystems Computer Company of Mountain View, Calif. have together agreed on and written a standard for a serial transceiver module, which is called the Gigabit Interface Converter (GBIC) module. The module provides a single small form factor for a wide variety of standard Fibre Channel connectors and transmission media. The module can be inserted in or removed from a host or switch chassis without first removing power from the receiving socket. Any copper and optical transmission technologies consistent with the form factor can be used.
The GBIC module has a plug in a first insulative housing and a receptacle in a second insulative housing at respective opposite ends of the module. A printed circuit board containing transceiver circuitry is secured to, and connects, the plug and the receptacle. The module is insertable into a guide structure mounted to a host board and having a receiving end and a terminating end. The terminating end of the guide structure has a receptacle for mating engagement with the module plug when the module is fully inserted in the guide structure. The guide structure houses and aligns the module and provides polarized guide rails to prevent incorrect installation of the module and is designed to accept the side retention latches specified in the GBIC module standard.
The standard for the GBIC module sets signal specifications for all positions of the module plug and receptacle. In particular, the GBIC module is driven from the host board with serial differential positive emitter coupled logic (PECL) signals applied to a pair of transmission data leads. There are two basic types of GBIC modules when the transmission medium is wire, rather than fiber. The passive GBIC module is for use when the length of the wire is up to about thirteen (13) meters. Thus, the passive GBIC module merely passes signals between the host and the transmission medium, without providing any signal processing or amplification. However, when the length of the wire is greater than about thirteen (13) meters, up to about thirty (30) meters, an active GBIC module is required to provide an appropriate power boost to the signals.
The serial receiver on the active GBIC module board detects incoming signals and amplifies and converts them to provide to the host board serial differential PECL data signals on a pair of receive data leads. Various control and status signals are also specified in the active GBIC module standard. For example, a receive loss of signal (RX_LOS) indication is generated when the incoming data signal amplitude is not sufficient to achieve the specified bit error rate or to indicate loss of power at the receiver circuit. A transmission fault signal is generated to indicate a failure has been detected in the transmission conversion circuit or to indicate loss of power at the transmit circuit. The output from the transmission conversion circuit is also disabled in response to a transmit disable signal generated by the host.
A typical application for a passive GBIC module is in a fiber channel arbitrated loop. In such a loop, there is a hub with multiple ports, each with a passive GBIC module. The hub interrogates the ports to see what is connected to each port. If the passive GBIC module is connected either to an open line or to a turned off terminal, crosstalk between the receive and transmit wires sends the interrogation signal back to the hub receiver at a very low level. The sensitivity of a hub receiver is typically 25 millivolts, whereas the GBIC specification calls for a minimum signal level of 400 millivolts. The crosstalk signal sent back to the hub could exceed the 25 millivolt sensitivity of the receiver, so that the receiver senses this signal and waits for a handshake which never arrives. Accordingly, the entire system freezes up. Until now, the passive GBIC module did not contain any active circuitry, its only function being to pass signals between the host and the transmission media. It would therefore be desirable to equip a passive GBIC module with circuitry for detecting when a received signal was below the minimum threshold called for in the GBIC specification so as to prevent the host from falsely responding to a low level signal.
A passive GBIC module is adapted for connection between a host and a transmission medium, with the module having a pair of receive circuit paths extending between a receptacle connectable to the transmission medium and a plug connectable to the host. Each of the pair of receive circuit paths includes a respective first series capacitor. According to the present invention, a signal detection circuit is connected to the pair of receive circuit paths and a respective second series capacitor is inserted in each of the receive circuit paths on the other side of the respective connection to the signal detection circuit from the respective first series capacitor.
In accordance with an aspect of this invention, the signal detection circuit comprises a current supply and an operational amplifier having an inverting input, a non-inverting input and an output. A first controllable switching element is coupled to the current supply and to the non-inverting input of the operational amplifier. A second controllable switching element is coupled to the current supply and to the inverting input of the operational amplifier. A third controllable switching element is coupled to the current supply and to the inverting input of the operational amplifier. The second controllable switching element has a control terminal coupled to a first of the pair of receive circuit paths and the third controllable switching element has a control terminal coupled to the other of the pair of receive circuit paths. The control terminals of the second and third controllable switching elements are further coupled to a fixed bias voltage and the control terminal of the first controllable switching element is coupled to a bias voltage equal to the fixed bias voltage plus one half the predetermined differential threshold. Accordingly, the output of the operational amplifier is at a first level when the differential between signals appearing on the pair of receive circuit paths exceeds the predetermined differential threshold and is at a second level when the differential between signals appearing on the pair of receive circuit paths is less than the predetermined differential threshold.